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[VHDL-FPGA-Verilog] uart_regs

Description: 可以直接下载到芯片用的带有FIFO的完全UART程序，vhdl语言编写。-Can be directly downloaded to the chip used in the complete UART with FIFO procedures, vhdl language.
Platform: | Size: 388096 | Author: liujingxing | Hits:

[source in ebook] VHDL

Description: 高质量的VHDL代码乒乓处理FIFO缓存-High-quality VHDL code deal with ping-pong FIFO cache
Platform: | Size: 1024 | Author: wode | Hits:

[VHDL-FPGA-Verilog] asynchronous-FIFO-structure

Description:
Platform: | Size: 545792 | Author: john | Hits:

[Other] fifo

Description: 一个FIFO设计的例子，例子简单，但很经典。 是学好数字设计的好开端。-A FIFO design examples, example of simple, but very classic. Learn digital design is a good start.
Platform: | Size: 1024 | Author: Benson | Hits:

[OS Develop] fifo

Description: 利用一个SAM设计一个FIFO 的存储器-SAM uses a design of a FIFO memory
Platform: | Size: 9216 | Author: lzc | Hits:

[Program doc] vhdlfi

Description: fifo vhdl源码，高可靠性，带有格雷码同步，有需要可依进行参考！-fifo vhdl source, high reliability, with Gray-code synchronization, there is a need-based reference!
Platform: | Size: 3072 | Author: lee | Hits:

[Embeded-SCM Develop] VHDL

Description: 常见的输入输出及存储器件（ram及fifo）vhdl实现-The vhdl source codes of ram,fifo.
Platform: | Size: 22528 | Author: xugx | Hits:

[VHDL-FPGA-Verilog] FIFO

Description: it is a verilog code written for FIFO in modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device].you can use this code in any DSP project in which data entry is required.-it is a verilog code written for FIFO in modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device].you can use this code in any DSP project in which data entry is required.
Platform: | Size: 31744 | Author: yasir ateeq | Hits:

[VHDL-FPGA-Verilog] connect20090223

Description: fpga从FIFO读数据并上传到双口ram中。-FPGA read data from the FIFO and upload it to dual-port ram Medium.
Platform: | Size: 468992 | Author: 张菁 | Hits:

[VHDL-FPGA-Verilog] FIFO

Description: This code is a FIFO memory vhdl developed in ISE Software
Platform: | Size: 3377152 | Author: Arley | Hits:

[OS Develop] program

Description: 设计实现4bit FIFO, 数据深度为8， 产生满， 空状态标志-The diagram of FIFO is shown in figure 1. The FIFO consists of two component: FIFO control logic and RAM. The control logic generates the address (ADD) and write enable (WE) to the RAM so that the first data word written into the RAM is also the first data word retrieved from the RAM. As shown in the Figure 1, the RAM is implemented to operate as a FIFO. The RAM is assumed to have separate data inputs and outputs, an N-bit address bus (ADD) and an active high write enable (WE). The inputs to FIFO/Stack include PUSH, POP, INIT (all active high) in addition to the rising edge triggered CLK input. The FIFO logic will not only supply the address and write enable to the RAM, but will also supply active high flags for FULL, EMPTY, NOPOP, and NOPUSH conditions.
Platform: | Size: 3072 | Author: shao | Hits:

[VHDL-FPGA-Verilog] fifo_vhdl

Description: FIFO的VHDL编程，其中包括FIFO的读，写，满帧，半满帧信号驱动-FIFO of the VHDL programming, including the FIFO' s read, write, full frame, half-full frame signal drive
Platform: | Size: 1024 | Author: 刘石 | Hits:

[OS Develop] fifodd

Description: 一个深度为32，字长为8_bit FIFO（先进先出）寄存器，有寄存器空、寄存器满和寄存器溢出信号。-A depth of 32, word length for 8_bit FIFO (FIFO) register, a register space, register and register full signal overflow.
Platform: | Size: 79872 | Author: tangyi | Hits:

[VHDL-FPGA-Verilog] fifo.vhd

Description: This a FIFO in VHDL Code-This is a FIFO in VHDL Code
Platform: | Size: 3072 | Author: lagartojj | Hits:

[VHDL-FPGA-Verilog] fifo1k_32

Description: PCI 数据采集控制卡的内部 FIFO处理代码-Data Acquisition and Control Card PCI internal FIFO handling code
Platform: | Size: 2048 | Author: dalchan | Hits:

[VHDL-FPGA-Verilog] fifo_sync

Description: 用VHDL语言编写的FPGA程序,实现异步FIFO的功能。这个程序设计十分巧妙，精简。 -vhdl fifo sound code
Platform: | Size: 1024 | Author: zxb | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: 包括用用VHDL语言编写的DDS,FIFO,交通控制灯，数字电压计，信号发生器的源码，希望能帮到大家-Including the use of VHDL language with the DDS, FIFO, traffic control lights, digital voltage, the signal generator of the source, I hope to help you
Platform: | Size: 69632 | Author: link | Hits:

[VHDL-FPGA-Verilog] FIFO

Description: 完整的FIFO完整源代码，通过仿真 完整的FIFO完整源代码，通过仿真 -Complete FIFO full source code, through the simulation of the complete FIFO full source code, through the simulation of
Platform: | Size: 3072 | Author: culun | Hits:

[VHDL-FPGA-Verilog] mem_ctrl_latest.tar

Description: 存储器控制FPGA程序，包括ram，fifo，sdram，flash等。-FPGA memory control processes, including ram, fifo, sdram, flash and so on.
Platform: | Size: 331776 | Author: zhangsan | Hits:

[VHDL-FPGA-Verilog] VHDLbasicExampleDEVELOPEMENTsoursE

Description: 这里收录的是《VHDL基础及经典实例开发》一书中12个大型实例的源程序。为方便读者使用，介绍如下： Chapter3：schematic和vhdl文件夹，分别是数字钟设计的原理图文件和VHDL程序； Chapter4：multiplier文件夹，串并乘法器设计程序（提示：先编译程序包）； Chapter5：sci文件夹，串行通信接口设计程序； Chapter6：watchdog文件夹，看门狗设计程序； Chapter7：taxi文件夹，出租车计价器设计程序； Chapter8：elevator文件夹，高层电梯控制器设计程序； Chapter9：cymometer1和cymometer2文件夹，前者是计数测频设计程序，后者是等精度测频设计程序； Chapter10：digital_lock文件夹，数字密码锁设计程序； Chapter11：I2C文件夹，I2C控制器设计程序； Chapter12：fifo文件夹，异步FIFO设计程序； Chapter13：dds文件夹，数字频率合成设计程序； Chapter14：vLA文件夹，虚拟逻辑分析仪设计程序。 -this book includes 12 detail examples of the source program
Platform: | Size: 139264 | Author: wuyu | Hits:
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